Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-20 Freescale Semiconductor
Table 9-12 describes the DDR_SDRAM_CFG fields.
Table 9-12. DDR_SDRAM_CFG Field Descriptions
Bits Name Description
0 MEM_EN DDR SDRAM interface logic enable.
0 SDRAM interface logic is disabled.
1 SDRAM interface logic is enabled. Must not be set until all other memory configuration
parameters have been appropriately configured by initialization code.
1 SREN Self refresh enable (during sleep).
0 SDRAM self refresh is disabled during sleep. Whenever self-refresh is disabled, the system is
responsible for preserving the integrity of SDRAM during sleep.
1 SDRAM self refresh is enabled during sleep.
2 ECC_EN ECC enable. Note that uncorrectable read errors may cause an interrupt.
0 No ECC errors are reported. No ECC interrupts are generated.
1 ECC is enabled.
3 RD_EN Registered DRAM module enable. Specifies the type of DRAM module used in the system.
0 Indicates unbuffered DRAM modules.
1 Indicates registered DRAM modules.
Note: RD_EN and 2T_EN must not both be set at the same time.
4 — Reserved
5–7 SDRAM_TYPE Type of SDRAM device to be used. This field is used when issuing the automatic hardware
initialization sequence to DRAM through Mode Register Set and Extended Mode Register Set
commands.
For DDR2 SDRAM, the field is set to 011.
8–9 — Reserved
10 DYN_PWR Dynamic power management mode
0 Dynamic power management mode is disabled.
1 Dynamic power management mode is enabled. If there is no ongoing memory activity, the
SDRAM CKE signal is negated.
11–12 DBW DRAM data bus width.
00 Reserved
01 32-bit bus is used
10 16-bit bus is used
11 Reserved
13 — Reserved
14 NCAP Non-concurrent auto-precharge. Some older DDR DRAMs do not support concurrent auto
precharge. If one of these devices is used, then this bit needs to be set if auto precharge is used.
0 DRAMs in system support concurrent auto-precharge.
1 DRAMs in system do not support concurrent auto-precharge.
15 — Reserved
16 2T_EN Enable 2T timing.
0 1T timing is enabled. The DRAM command/address are held for only 1 cycle on the DRAM bus.
1 2T timing is enabled. The DRAM command/address are held for 2 full cycles on the DRAM bus
for every DRAM transaction. However, the chip select is only held for the second cycle.
Note: RD_EN and 2T_EN must not both be set at the same time.