Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-19
9.4.1.7 DDR SDRAM Control Configuration (DDR_SDRAM_CFG)
The DDR SDRAM control configuration register, shown in Figure 9-8, enables the interface logic and
specifies certain operating features such as self refreshing, error checking and correcting, registered
DIMMs, and dynamic power management.
13–15 — Reserved
16–18 RD_TO_PRE Read to precharge (t
RTP
). For DDR2, with a non-zero ADD_LAT value, takes a minimum of
ADD_LAT + t
RTP
cycles between read and precharge.
000 Reserved
001 1 cycle
010 2 cycles
011 3 cycles
100 4 cycles
101–111 Reserved
19–21 WR_DATA_DELAY Write command to write data strobe timing adjustment. Controls the amount of delay applied to the
data and data strobes for writes. See Section 9.5.7, “DDR SDRAM Write Timing Adjustments,” for
details.
000 0 clock delay
001 1/4 clock delay
010 1/2 clock delay
011 3/4 clock delay
100 1 clock delay
101 5/4 clock delay
110 3/2 clock delay
111 Reserved
22 — Reserved
23–25 CKE_PLS Minimum CKE pulse width (t
CKE
).
000 Reserved
001 1 cycle
010 2 cycles
011 3 cycles
100 4 cycles
101–111 Reserved
26–31 FOUR_ACT Window for four activates (t
FAW
). This is applied to DDR2 with eight logical banks only.
000000 Reserved
0000011 cycle
0000102 cycles
0000113 cycles
0001004 cycles
...
010011 19 cycles
01010020 cycles
010101–111111 Reserved
Offset 0x110 Access: Read/Write
012345 789101112131415
R
MEM_EN SREN ECC_EN RD_EN — SDRAM_TYPE —
DYN
_P
WR
DBW — NCAP —
W
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
16 17 23 24 26 27 28 29 30 31
R
2T_EN BA_INTLV_CTL — PCHB8 HSE — MEM_HALT BI
W
Reset All zeros
Figure 9-8. DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG)
Table 9-11. TIMING_CFG_2 Field Descriptions (continued)
Bits Name Description