Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-18 Freescale Semiconductor
9.4.1.6 DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)
DDR SDRAM timing configuration 2, shown in Figure 9-7, sets the clock delay to data for writes.
Table 9-11 describes the TIMING_CFG_2 fields.
Offset 0x10C Access: Read/Write
0 1 3 4 8 9 10 12 13 15 16 18 19 21 22 23 25 26 31
R
— ADD_LAT CPO — WR_LAT — RD_TO_PRE WR_DATA_DELAY — CKE_PLS FOUR_ACT
W
Reset All zeros
Figure 9-7. DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2)
Table 9-11. TIMING_CFG_2 Field Descriptions
Bits Name Description
0 — Reserved
1–3 ADD_LAT Additive latency. The additive latency must be set to a value less than TIMING_CFG_1[ACTTORW].
000 0 clocks
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 Reserved
111 Reserved
4–8 CPO MCAS
-to-preamble override. Defines the number of DRAM cycles between when a read is issued
and when the corresponding DQS preamble is valid for the memory controller. For these decodings,
“READ_LAT” is equal to the CAS latency plus the additive latency.
00000READ_LAT + 1
00001Reserved
00010READ_LAT
00011READ_LAT + 1/4
00100READ_LAT + 1/2
00101READ_LAT + 3/4
00110READ_LAT + 1
00111READ_LAT + 5/4
01000READ_LAT + 3/2
01001READ_LAT + 7/4
01010READ_LAT + 2
01011READ_LAT + 9/4
01100READ_LAT + 5/2
01101READ_LAT + 11/4
01110READ_LAT + 3
01111READ_LAT + 13/4
10000READ_LAT + 7/2
10001READ_LAT + 15/4
10010READ_LAT + 4
10011READ_LAT + 17/4
10100READ_LAT + 9/2
10101READ_LAT + 19/4
10110–11111 Reserved
9 — Reserved
10–12 WR_LAT Write latency. Note that the total write latency for DDR2 is equal to WR_LAT + ADD_LAT.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks