Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-17
12–15 CASLAT MCAS
latency from READ command. Number of clock cycles between registration of a READ command
by the SDRAM and the availability of the first output data. If a READ command is registered at clock edge
n and the latency is m clocks, data is available nominally coincident with clock edge n + m. This value
must be programmed at initialization as described in Section 9.4.1.8, “DDR SDRAM Control Configuration
2 (DDR_SDRAM_CFG_2).”)
0000 Reserved
0001 Reserved
0010 Reserved
0011 Reserved
0100 Reserved
0101 3 clocks
0110 3.5 clocks
0111 4 clocks
1000 4.5 clocks
1001 5 clocks
1010 5.5 clocks
1011 6 clocks
1100 6.5 clocks
1101 7 clocks
1110 7.5 clocks
1111 8 clocks
16–19 REFREC Refresh recovery time (t
RFC
). Controls the number of clock cycles from a refresh command until an activate
command is allowed. This field is concatenated with TIMING_CFG_3[EXTREFREC] to obtain a 7-bit value
for the total refresh recovery. Note that hardware adds an additional 8 clock cycles to the final, 7-bit value
of the refresh recovery, such that t
RFC
is calculated as follows: t
RFC
= {EXT_REFREC || REFREC} + 8.
0000 8 clocks
0001 9 clocks
0010 10 clocks
0011 11 clocks
…
1111 23 clocks
20 — Reserved, should be cleared.
21–23 WRREC Last data to precharge minimum interval (t
WR
). Determines the number of clock cycles from the last data
associated with a write command until a precharge command is allowed.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
24 — Reserved, should be cleared.
25–27 ACTTOACT Activate-to-activate interval (t
RRD
). Number of clock cycles from an activate command until another
activate command is allowed for a different logical bank in the same physical bank (chip select).
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
28 — Reserved, should be cleared.
29–31 WRTORD Last write data pair to read command issue interval (t
WTR
). Number of clock cycles between the last write
data pair and the subsequent read command to the same physical bank.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
Table 9-10. TIMING_CFG_1 Field Descriptions (continued)
Bits Name Description