Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor xxxiii
Figures
Figure
Number Title
Page
Number
16-33 RBASE Register Definition................................................................................................ 16-60
16-34 TMR_RXTS_H/L Register Definition................................................................................ 16-61
16-35 MACCFG1 Register Definition.......................................................................................... 16-64
16-36 MACCFG2 Register Definition.......................................................................................... 16-66
16-37 IPGIFG Register Definition................................................................................................ 16-68
16-38 Half-Duplex Register Definition......................................................................................... 16-69
16-39 Maximum Frame Length Register Definition..................................................................... 16-70
16-40 MII Management Configuration Register Definition ......................................................... 16-70
16-41 MIIMCOM Register Definition.......................................................................................... 16-71
16-42 MIIMADD Register Definition .......................................................................................... 16-72
16-43 MII Mgmt Control Register Definition............................................................................... 16-72
16-44 MIIMSTAT Register Definition.......................................................................................... 16-73
16-45 MII Mgmt Indicator Register Definition ............................................................................ 16-73
16-46 Interface Status Register Definition.................................................................................... 16-74
16-47 MAC Station Address Part 1 Register Definition............................................................... 16-74
16-48 MAC Station Address Part 2 Register Definition............................................................... 16-75
16-49 MAC Exact Match Address n Part 1 Register Definition................................................... 16-76
16-50 MAC Exact Match Address x Part 2 Register Definition ................................................... 16-76
16-51 Transmit and Receive 64-Byte Frame Register Definition................................................. 16-78
16-52 Transmit and Receive 65- to 127-Byte Frame Register Definition .................................... 16-78
16-53 Transmit and Received 128- to 255-Byte Frame Register Definition ................................ 16-79
16-54 Transmit and Received 256- to 511-Byte Frame Register Definition................................. 16-79
16-55 Transmit and Received 512- to 1023-Byte Frame Register Definition .............................. 16-80
16-56 Transmit and Received 1024- to 1518-Byte Frame Register Definition ............................ 16-80
16-57 Transmit and Received 1519- to 1522-Byte VLAN Frame Register Definition ................ 16-81
16-58 Receive Byte Counter Register Definition.......................................................................... 16-81
16-59 Receive Packet Counter Register Definition ...................................................................... 16-81
16-60 Receive FCS Error Counter Register Definition................................................................. 16-82
16-61 Receive Multicast Packet Counter Register Definition ...................................................... 16-82
16-62 Receive Broadcast Packet Counter Register Definition ..................................................... 16-83
16-63 Receive Control Frame Packet Counter Register Definition.............................................. 16-83
16-64 Receive Pause Frame Packet Counter Register Definition................................................. 16-84
16-65 Receive Unknown OPCode Packet Counter Register Definition....................................... 16-84
16-66 Receive Alignment Error Counter Register Definition....................................................... 16-85
16-67 Receive Frame Length Error Counter Register Definition ................................................. 16-85
16-68 Receive Code Error Counter Register Definition ............................................................... 16-86
16-69 Receive Carrier Sense Error Counter Register Definition.................................................. 16-86
16-70 Receive Undersize Packet Counter Register Definition ..................................................... 16-87
16-71 Receive Oversize Packet Counter Register Definition ....................................................... 16-87
16-72 Receive Fragments Counter Register Definition ................................................................ 16-88
16-73 Receive Jabber Counter Register Definition....................................................................... 16-88