Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-15
9–11 ACT_PD_EXIT Active powerdown exit timing (t
XARD
and t
XARDS
). Specifies how many clock cycles to wait after
exiting active powerdown before issuing any command.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
12 — Reserved, should be cleared.
13–15 PRE_PD_EXIT Precharge powerdown exit timing (t
XP
). Specifies how many clock cycles to wait after exiting
precharge powerdown before issuing any command.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
16–19 — Reserved, should be cleared.
20–23 ODT_PD_EXIT ODT powerdown exit timing (t
AXPD
). Specifies how many clocks must pass after exiting powerdown
before ODT may be asserted.
0000 0 clock
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
1000 8 clocks
1001 9 clocks
1010 10 clocks
1011 11 clocks
1100 12 clocks
1101 13 clocks
1110 14 clocks
1111 15 clocks
24–27 — Reserved, should be cleared.
28–31 MRS_CYC Mode register set cycle time (t
MRD
). Specifies the number of cycles that must pass after a Mode
Register Set command until any other command.
0000 Reserved
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
1000 8 clocks
1001 9 clocks
1010 10 clocks
1011 11 clocks
1100 12 clocks
1101 13 clocks
1110 14 clocks
1111 15 clocks
Table 9-9. TIMING_CFG_0 Field Descriptions (continued)
Bits Name Description