Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-14 Freescale Semiconductor
9.4.1.4 DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
DDR SDRAM timing configuration register 0, shown in Figure 9-5, sets the number of clock cycles
between various SDRAM control commands.
Table 9-9 describes TIMING_CFG_0 fields.
Offset 0x104 Access: Read/Write
0 1 2 3 4 5 6 7 8 9 11 12 13 15 16 19 20 23 24 27 28 31
R
RWT WRT RRT WWT — ACT_PD_EXIT — PRE_PD_EXIT — ODT_PD_EXIT — MRS_CYC
W
Reset000000000 0 0 1 0 0 0 10000000100000101
Figure 9-5. DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
Table 9-9. TIMING_CFG_0 Field Descriptions
Bits Name Description
0–1 RWT Read-to-write turnaround (t
RTW
). Specifies how many extra cycles are added between a read to write
turnaround. If 0 clocks is chosen, then the DDR controller uses a fixed number based on the CAS
latency and write latency. Choosing a value other than 0 adds extra cycles past this default
calculation. As a default the DDR controller determines the read-to-write turnaround as CL – WL +
BL  2 + 2. In this equation, CL is the CAS latency rounded up to the next integer, WL is the
programmed write latency, and BL is the burst length.
00 0 clocks
01 1 clock
10 2 clocks
11 3 clocks
2–3 WRT Write-to-read turnaround. Specifies how many extra cycles are added between a write to read
turnaround. If 0 clocks is chosen, then the DDR controller uses a fixed number based on the, read
latency, and write latency. Choosing a value other than 0 adds extra cycles past this default
calculation. As a default, the DDR controller determines the write-to-read turnaround as WL – CL +
BL  2 + 1. In this equation, CL is the CAS latency rounded down to the next integer, WL is the
programmed write latency, and BL is the burst length.
00 0 clocks
01 1 clock
10 2 clocks
11 3 clocks
4–5 RRT Read-to-read turnaround. Specifies how many extra cycles are added between reads to different
chip selects. As a default, 3 cycles are required between read commands to different chip selects.
Extra cycles may be added with this field. Note: If 8-beat bursts are enabled, then 5 cycles are the
default. Note that DDR2 does not support 8-beat bursts.
00 0 clocks
01 1 clock
10 2 clocks
11 3 clocks
6–7 WWT Write-to-write turnaround. Specifies how many extra cycles are added between writes to different
chip selects. As a default, 2 cycles are required between write commands to different chip selects.
Extra cycles may be added with this field. Note: If 8-beat bursts are enabled, then 4 cycles are the
default. Note that DDR2 does not support 8-beat bursts.
00 0 clocks
01 1 clock
10 2 clocks
11 3 clocks
8 — Reserved, should be cleared.