Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-13
9.4.1.3 DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)
DDR SDRAM timing configuration register 3, shown in Figure 9-4, sets the extended refresh recovery
time, which is combined with TIMING_CFG_1[REFREC] to determine the full refresh recovery time.
Table 9-8 describes TIMING_CFG_3 fields.
18–20 — Reserved
21–23 ROW_BITS_CS_n Number of row bits for SDRAM on chip select n. See Table 9- 38 for details.
000 12 row bits
001 13 row bits
010 14 row bits
011–111 Reserved
24–28 — Reserved
29–31 COL_BITS_CS_n Number of column bits for SDRAM on chip select n. For DDR, the decoding is as follows:
000 8 column bits
001 9 column bits
010 10 column bits
011 11 column bits
100–111 Reserved
Offset 0x100 Access: Read/Write
012131516 31
R
—
EXT_REFRE
C
—
W
Reset All zeros
Figure 9-4. DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)
Table 9-8. TIMING_CFG_3 Field Descriptions
Bits Name Description
0–12 — Reserved, should be cleared.
13–15 EXT_REFREC Extended refresh recovery time (t
RFC
). Controls the number of clock cycles from a refresh command
until an activate command is allowed. This field is concatenated with TIMING_CFG_1[REFREC] to
obtain a 7-bit value for the total refresh recovery. Note that hardware adds an additional 8 clock
cycles to the final, 7-bit value of the refresh recovery. t
RFC
= {EXT_REFREC || REFREC} + 8, such
that t
RFC
is calculated as follows:
000 0 clocks
001 16 clocks
010 32 clocks
011 48 clocks
100 64 clocks
101 80 clocks
110 96 clocks
111 112 clocks
16–31 — Reserved, should be cleared.
Table 9-7. CSn_CONFIG Field Descriptions (continued)
Bits Name Description