Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-12 Freescale Semiconductor
For example, if chip selects 0 and 1 are interleaved, all fields in CS0_CONFIG are used, but only the
ODT_RD_CFG and ODT_WR_CFG fields in CS1_CONFIG are used.
Table 9-7 describes the CSn_CONFIG register fields.
Offset 0x080, 0x084 Access: Read/Write
01 78 9 111213 15
R
CS_n _EN — AP_n_EN ODT_RD_CFG — ODT_WR_CFG
W
Reset All zeros
16 17 18 20 21 23 24 28 29 31
R
BA_BITS_CS_n — ROW_BITS_CS_n — COL_BITS_CS_n
W
Reset All zeros
Figure 9-3. Chip Select Configuration Register (CSn_CONFIG)
Table 9-7. CSn_CONFIG Field Descriptions
Bits Name Description
0 CS_n_EN Chip select n enable
0 Chip select n is not active
1 Chip select n is active and assumes the state set in CSn_BNDS.
1–7 — Reserved
8 AP_n_EN Chip select n auto-precharge enable
0 Chip select n is only auto-precharged if global auto-precharge mode is enabled
(DDR_SDRAM_INTERVAL[BSTOPRE] = 0).
1 Chip select n always issues an auto-precharge for read and write transactions.
9–11 ODT_RD_CFG ODT for reads configuration. Note that CAS latency plus additive latency must be at least
3 cycles for ODT_RD_CFG to be enabled.
000 Never assert ODT for reads
001 Assert ODT only during reads to CSn
010 Assert ODT only during reads to other chip selects
011 Reserved
100 Assert ODT for all reads
101–111Reserved
12 — Reserved
13–15 ODT_WR_CFG ODT for writes configuration. Note that write latency plus additive latency must be at least
3 cycles for ODT _WR_CFG to be enabled.
000 Never assert ODT for writes
001 Assert ODT only during writes to CSn
010 Assert ODT only during writes to other chip selects
011 Reserved
100 Assert ODT for all writes
101–111Reserved
16–17 BA_BITS_CS_n Number of bank bits for SDRAM on chip select n. These bits correspond to the sub-bank bits
driven on MBAn in Tabl e 9- 38.
00 2 logical bank bits
01 3 logical bank bits
10–11Reserved