Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-11
If chip select interleaving is enabled, all fields in the lower interleaved chip select are used, and the other
chip selects’ bounds registers are unused. For example, if chip selects 0 and 1 are interleaved, all fields in
CS0_BNDS are used, and all fields in CS1_BNDS are unused.
CSn_BNDS are shown in Figure 9-2.
Table 9-6 describes the CSn_BNDS register fields.
9.4.1.2 Chip Select Configuration (CSn_CONFIG)
The chip select configuration (CSn_CONFIG) registers shown in Figure 9-3 enable the DDR chip selects
and set the number of row and column bits used for each chip select. These registers should be loaded with
the correct number of row and column bits for each SDRAM. Because CSn_CONFIG[ROW_BITS_CS_n,
COL_BITS_CS_n] establish address multiplexing, the user should take great care to set these values
correctly.
If chip select interleaving is enabled, then all fields in the lower interleaved chip select are used, and the
other registers’ fields are unused, with the exception of the ODT_RD_CFG and ODT_WR_CFG fields.
Offset 0x000, 0x008 Access: Read/Write
0 78 1516232431
R
—SAn —EAn
W
Reset All zeros
Figure 9-2. Chip Select Bounds Registers (CSn_BNDS)
Table 9-6. CSn_BNDS Field Descriptions
Bits Name Description
0–7 — Reserved
8–15 SAn Starting address for chip select (bank) n. This value is compared against the 8 msbs of the 32-bit address.
16–23 — Reserved
24–31 EAn Ending address for chip select (bank) n. This value is compared against the 8 msbs of the 32-bit address.