Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-9
9.3.2.2 Clock Interface Signals
Table 9-4 contains the detailed descriptions of the clock signals of the DDR controller.
9.4 Memory Map/Register Definition
Table 9-5 shows the register memory map for the DDR memory controller.
In this table and in the register figures and field descriptions, the following access definitions apply:
• Reserved fields are always ignored for the purposes of determining access type.
• R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
• w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
• Mixed indicates a combination of access types.
• Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
Table 9-4. Clock Signals—Detailed Signal Descriptions
Signal I/O Description
MCK[0:2],
MCK
[0:2]
O DRAM clock output and its complement. See Section 9.5.4.1, “Clock Distribution.”
State
Meaning
Asserted/Negated—The JEDEC DDR SDRAM specifications require true and complement
clocks. A clock edge is seen by the SDRAM when the true and complement cross.
Timing Assertion/Negation—Timing is controlled by the DDR_CLK_CNTL register at offset 0x130.
MCKE O Clock enable. Output signals used as the clock enables to the SDRAM. MCKE can be negated to stop
clocking the DDR SDRAM.
State
Meaning
Asserted—Clocking to the SDRAM is enabled.
Negated—Clocking to the SDRAM is disabled and the SDRAM should ignore signal transitions
on MCK or MCK. MCK/MCK are don’t cares while MCKE is negated.
Timing Assertion/Negation—Asserted when DDR_SDRAM_CFG[MEM_EN] is set. Can be negated
when entering dynamic power management or self refresh. Are asserted again when
exiting dynamic power management or self refresh.
High impedance—Always driven.
Table 9-5. DDR Memory Controller Memory Map
Offset Register Access Reset Section/Page
DDR Memory Controller—Block Base Address 0x0_2000
0x000 CS0_BNDS—Chip select 0 memory bounds R/W 0x0000_0000 9.4.1.1/9-10
0x008 CS1_BNDS—Chip select 1 memory bounds R/W 0x0000_0000 9.4.1.1/9-10
0x080 CS0_CONFIG—Chip select 0 configuration R/W 0x0000_0000 9.4.1.2/9-11
0x084 CS1_CONFIG—Chip select 1 configuration R/W 0x0000_0000 9.4.1.2/9-11
0x100 TIMING_CFG_3—DDR SDRAM timing configuration 3 R/W 0x0000_0000 9.4.1.3/9-13
0x104 TIMING_CFG_0—DDR SDRAM timing configuration 0 R/W 0x0011_0105 9.4.1.4/9-14
0x108 TIMING_CFG_1—DDR SDRAM timing configuration 1 R/W 0x0000_0000 9.4.1.5/9-16
0x10C TIMING_CFG_2—DDR SDRAM timing configuration 2 R/W 0x0000_0000 9.4.1.6/9-18