Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-8 Freescale Semiconductor
MRAS
O Row address strobe. Active-low SDRAM address multiplexing signal. Asserted for activate commands.
In addition; used for mode register set commands and refresh commands.
State
Meaning
Asserted—Indicates that a valid SDRAM row address is on the address bus for read and
write transactions. See Tabl e 9-41 for more information on the states required on MRAS
for various other SDRAM commands.
Negated—The row address is not guaranteed to be valid.
Timing Assertion/Negation—Assertion and negation timing is directed by the values described in
Section 9.4.1.4, “DDR SDRAM Timing Configuration 0 (TIMING_CFG_0),”
Section 9.4.1.5, “DDR SDRAM Timing Configuration 1 (TIMING_CFG_1),”
Section 9.4.1.6, “DDR SDRAM Timing Configuration 2 (TIMING_CFG_2),” and
Section 9.4.1.3, “DDR SDRAM Timing Configuration 3 (TIMING_CFG_3).”
High impedance—MRAS
is always driven unless the memory controller is disabled.
MCS[0:1] O Chip selects. Two chip selects supported by the memory controller.
State
Meaning
Asserted—Selects a physical SDRAM bank to perform a memory operation as described in
Section 9.4.1.1, “Chip Select Memory Bounds (CSn_BNDS),” and Section 9.4.1.2,
“Chip Select Configuration (CSn_CONFIG).” The DDR controller asserts one of the
MCS[0:1] signals to begin a memory cycle.
Negated—Indicates no SDRAM action during the current cycle.
Timing Assertion/Negation—Asserted to signal any new transaction to the SDRAM. The transaction
must adhere to the timing constraints set in TIMING_CFG_0–TIMING_CFG_3.
High impedance—Always driven unless the memory controller is disabled.
MWE
O Write enable. Asserted when a write transaction is issued to the SDRAM. This is also used for mode
registers set commands and precharge commands.
State
Meaning
Asserted—Indicates a memory write operation. See Table 9 -4 1 for more information on the
states required on MWE for various other SDRAM commands.
Negated—Indicates a memory read operation.
Timing Assertion/Negation—Similar timing as MRAS and MCAS. Used for write commands.
High impedance—MWE is always driven unless the memory controller is disabled.
MDM[0:3],
MDM[8]
O DDR SDRAM data output mask. Masks unwanted bytes of data transferred during a write. They are
needed to support sub-burst-size transactions (such as single-byte writes) on SDRAM where all I/O
occurs in multi-byte bursts. MDM0 corresponds to the most significant byte (MSB) and MDM3
corresponds to the LSB, while MDM4 corresponds to the ECC byte. Tabl e 9- 36 shows byte lane
encodings.
State
Meaning
Asserted—Prevents writing to DDR SDRAM. Asserted when data is written to DRAM if the
corresponding byte(s) should be masked for the write. Note that the MDMn signals are
active-high for the DDR controller. MDMn is part of the DDR command encoding.
Negated—Allows the corresponding byte to be written to the SDRAM.
Timing Assertion/Negation—Same timing as MDQx as outputs.
High-impedance—Always driven unless the memory controller is disabled.
MODT[0:1] O On-Die termination. Memory controller outputs for the ODT to the DRAM. MODT[0:1] represents the
on-die termination for the associated data, data masks, ECC, and data strobes.
State
Meaning
Asserted/Negated—Represents the ODT driven by the DDR memory controller.
Timing Assertion/Negation—Driven in accordance with JEDEC DRAM specifications for on-die
termination timings. It is configured through the CSn_CONFIG[ODT_RD_CFG] and
CSn_CONFIG[ODT_WR_CFG] fields.
High impedance—Always driven.
Table 9-3. Memory Interface Signals—Detailed Signal Descriptions (continued)
Signal I/O Description