Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-7
MECC[0:7] I/O Error checking and correcting codes. Input and output signals for the DDR controller’s bidirectional ECC
bus. MECC[0:5] function in both normal and debug modes.
O ECC signals represent the state of ECC driven by the DDR controller on writes. See Section 9.5.11,
“Error Checking and Correcting (ECC),” for more details.
State
Meaning
Asserted/Negated—Represents the state of ECC being driven by the DDR controller on
writes.
Timing Assertion/Negation—Same timing as MDQ
High impedance—Same timing as MDQ
I As inputs, the ECC signals represent the state of ECC driven by the SDRAM devices on reads.
State
Meaning
Asserted/Negated—Represents the state of ECC being driven by the DDR SDRAMs on
reads.
Timing Assertion/Negation—Same timing as MDQ
High impedance—Same timing as MDQ
MA[13:0] O Address bus. Memory controller outputs for the address to the DRAM. MA[13:0] carry 14 of the address
bits for the DDR memory interface corresponding to the row and column address bits. MA0 is the lsb of
the address output from the memory controller.
State
Meaning
Asserted/Negated—Represents the address driven by the DDR memory controller. Contains
different portions of the address depending on the memory size and the DRAM
command being issued by the memory controller. See Tabl e 9 -3 8 for a complete
description of the mapping of these signals.
Timing Assertion/Negation—The address lines are only driven when the controller has a command
scheduled to issue on the address/CMD bus; otherwise they will be at high-Z. It is valid
when a transaction is driven to DRAM (when MCS
n is active).
High impedance—When the memory controller is disabled
MBA[2:0] O Logical bank address. Outputs that drive the logical (or internal) bank address pins of the SDRAM. Each
SDRAM supports four or eight addressable logical sub-banks. Bit zero of the memory controller’s output
bank address must be connected to bit zero of the SDRAM’s input bank address. MBA0, the
least-significant bit of the three bank address signals, is asserted during the mode register set command
to specify the extended mode register.
State
Meaning
Asserted/Negated—Selects the DDR SDRAM logical (or internal) bank to be activated during
the row address phase and selects the SDRAM internal bank for the read or write
operation during the column address phase of the memory access. Tabl e 9- 38
describes the mapping of these signals in all cases.
Timing Assertion/Negation—Same timing as MAn
High impedance—Same timing as MAn
MCAS
O Column address strobe. Active-low SDRAM address multiplexing signal. MCAS is asserted for read or
write transactions and for mode register set, refresh, and precharge commands.
State
Meaning
Asserted—Indicates that a valid SDRAM column address is on the address bus for read and
write transactions. See Tabl e 9-41 for more information on the states required on MCAS
for various other SDRAM commands.
Negated—The column address is not guaranteed to be valid.
Timing Assertion/Negation—Assertion and negation timing is directed by the values described in
Section 9.4.1.4, “DDR SDRAM Timing Configuration 0 (TIMING_CFG_0),”
Section 9.4.1.5, “DDR SDRAM Timing Configuration 1 (TIMING_CFG_1),”
Section 9.4.1.6, “DDR SDRAM Timing Configuration 2 (TIMING_CFG_2),” and
Section 9.4.1.3, “DDR SDRAM Timing Configuration 3 (TIMING_CFG_3).”
High impedance—MCAS
is always driven unless the memory controller is disabled.
Table 9-3. Memory Interface Signals—Detailed Signal Descriptions (continued)
Signal I/O Description