Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
xxxii Freescale Semiconductor
Figures
Figure
Number Title
Page
Number
14-143 n-Way Chain Descriptor Organization in Host Memory .................................................. 14-132
14-144 Block Descriptor Organization in Host Memory.............................................................. 14-133
15-1 SerDes PHY Block Diagram................................................................................................. 15-1
15-2 SerDes Control Register 0 (SRDSCR0)................................................................................ 15-4
15-3 SerDesn Control Register 1 (SRDSnCR1)............................................................................ 15-6
15-4 SerDes Control Register 2 (SRDSCR2)................................................................................ 15-7
15-5 SerDes Control Register 3 (SRDSCR3)................................................................................ 15-8
15-6 SerDes Control Register 4 (SRDSCR4)................................................................................ 15-9
15-7 SerDes Reset Control Register (SRDSRSTCTL) ............................................................... 15-10
16-1 eTSEC Block Diagram.......................................................................................................... 16-2
16-2 TSEC_ID Register .............................................................................................................. 16-21
16-3 TSEC_ID2 Register ............................................................................................................ 16-22
16-4 IEVENT Register Definition .............................................................................................. 16-23
16-5 IMASK Register Definition................................................................................................ 16-27
16-6 EDIS Register Definition.................................................................................................... 16-28
16-7 ECNTRL Register Definition ............................................................................................. 16-30
16-8 PTV Register Definition...................................................................................................... 16-32
16-9 DMACTRL Register........................................................................................................... 16-32
16-10 TBIPA Register Definition.................................................................................................. 16-34
16-11 TCTRL Register Definition ................................................................................................ 16-34
16-12 TSTAT Register Definition ................................................................................................. 16-36
16-13 DFVLAN Register Definition............................................................................................. 16-40
16-14 TXIC Register Definition.................................................................................................... 16-41
16-15 TQUEUE Register Definition............................................................................................. 16-42
16-16 TR03WT Register Definition.............................................................................................. 16-43
16-17 TR47WT Register Definition.............................................................................................. 16-43
16-18 TBPTR0–TBPTR7 Register Definition .............................................................................. 16-44
16-19 TBASE Register Definition ................................................................................................ 16-45
16-20 TMR_TXTSn_ID Register Definition................................................................................ 16-45
16-21 TMR_TXTSn_H/L Register Definition.............................................................................. 16-46
16-22 RCTRL Register Definition................................................................................................
16-46
16-23 RSTAT Register Definition................................................................................................. 16-49
16-24 RXIC Register Definition ................................................................................................... 16-50
16-25 RQUEUE Register Definition............................................................................................. 16-51
16-26 RBIFX Register Definition ................................................................................................. 16-52
16-27 Receive Queue Filer Table Address Register Definition .................................................... 16-54
16-28 Receive Queue Filer Table Control Register Definition..................................................... 16-54
16-29 Receive Queue Filer Table Property IDs 0, 2–15 Register Definition................................ 16-55
16-30 Receive Queue Filer Table Property ID1 Register Definition ............................................ 16-56
16-31 MRBLR Register Definition............................................................................................... 16-59
16-32 RBPTR0–RBPTR7 Register Definition.............................................................................. 16-60