Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-5
Table 9-2 shows the memory address signal mappings.
Table 9-2. Memory Address Signal Mappings
Signal Name (Outputs) JEDEC DDR DIMM Signals (Inputs)
msb MA13 A13
MA12 A12
MA11 A11
MA10 A10 (AP for DDR)
1
1
Auto-precharge for DDR signaled on A10 when DDR_SDRAM_CFG[PCHB8] = 0
MA9 A9
MA8 A8 (alternate AP for DDR)
2
2
Auto-precharge for DDR signaled on A8 when DDR_SDRAM_CFG[PCHB8] = 1
MA7 A7
MA6 A6
MA5 A5
MA4 A4
MA3 A3
MA2 A2
MA1 A1
lsb MA0 A0
msb MBA2 MBA2
MBA1 MBA1
lsb MBA0 MBA0