Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-4 Freescale Semiconductor
Table 9-1 shows how DDR memory controller external signals are grouped. The device hardware
specification has a pinout diagram showing pin numbers. It also lists all electrical and mechanical
specifications.
Table 9-1. DDR Memory Interface Signal Summary
Name Function/Description Reset Pins I/O
MDQ[0:31] Data bus All zeros 32 I/O
MDQS[0:3] Data strobes All zeros 4 I/O
MDQS[8] Data strobe for MECC[0:7] All zeros 1 I/O
MECC[0:7] Error checking and correcting All zeros 8 I/O
MCAS Column address strobe One 1 O
MA[13:0] Address bus All zeros 14 O
MBA[2:0] Logical bank address All zeros 3 O
MCS[0:1] Chip selects All ones 2 O
MWE Write enable One 1 O
MRAS Row address strobe One 1 O
MDM[0:3] Data mask All zeros 4 O
MDM[8] Data mask for MECC[0:7] All zeros 1 O
MCK[0:2] DRAM clock outputs Zero 3 O
MCK[0:2] DRAM clock outputs (complement) One 3 O
MCKE DRAM clock enable Zero 1 O
MODT[0:1] DRAM on-die termination external control. All zeros 2 O
MV
REF
DDR2 DRAM reference — 1 I