Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-2 Freescale Semiconductor
Figure 9-1 is a high-level block diagram of the DDR memory controller with its associated interfaces.
Section 9.5, “Functional Description,” contains detailed figures of the controller.
Figure 9-1. DDR Memory Controller Simplified Block Diagram
9.2 Features
The DDR memory controller includes these distinctive features:
• Support for DDR2 SDRAM
• Supports 8-bit ECC
• Supports 16-/32-bit data interface
• Programmable settings for meeting all SDRAM timing parameters
• The following SDRAM configurations are supported:
— As many as two physical banks (chip selects), each bank independently addressable upto
512 Mbytes
– 64-Mbit to 2-Gbit devices depending on internal device configuration with 8/16/32 data
ports (no direct 4 support)
– One 32-bit device, one 16-bit device or two 8-bit devices on a 16-bit bus, or two 16-bit
devices or four 8-bit devices on a 32-bit bus
Address from
DDR SDRAM
Data from
Data from
DDR SDRAM
Data Signals
RMW
ECC
Request from
FIFO
SDRAM
Address
Address
EN
Data Qualifiers
Clocks
To error
MBA[2:0]
MCAS
MRAS
MWE
MDM[0:3]
MDQS[0:3]
MECC[0:7]
MCK[0:2]
Decode
Control
Control
Memory Array
Memory Control
master
master
SDRAM
master
management
MCK[0:2]
CSB
ECC
Delay chain
Error
Signals
SDRAM
Control
Clock
Control
EN
Row
Open
Ta ble
MA[13:0]
MCKE
MDQ[0:31]
MCS
[0:1]
MODT[0:1]
MDM[8]
MDQS[8]