Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-1
Chapter 9
DDR Memory Controller
9.1 Introduction
The fully programmable DDR SDRAM controller supports most JEDEC standard 8, 16, and 32 DDR2
memories available. In addition, unbuffered and registered DIMMs are supported. However, mixing
different memory types or unbuffered and registered DIMMs in the same system is not supported. Built-in
error checking and correction (ECC) ensures very low bit-error rates for reliable high-frequency operation.
Dynamic power management and auto-precharge modes simplify memory system design. A large set of
special features, including ECC error injection, support rapid system debug.
NOTE
• In this chapter, the word ‘bank’ refers to a physical bank specified by a
chip select; ‘logical bank’ refers to one of the four or eight sub-banks in
each SDRAM chip. A sub-bank is specified by the 2 or 3 bits on the bank
address (MBA) pins during a memory access.
• MPC8308 supports only DDR2 controller. In this chapter, usage of the
word ‘DDR’ is generic and refers to the DDR2 controller.