Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 8-43
Figure 8-33 shows the message shared interrupt index register.
Table 8-39 describes the bits of the MSIIRs.
Offset 0xF8 Access: Write only
023 78 31
R
—
WSRS IBS
Reset All zeros
Figure 8-33. Message Shared Interrupt Index Register (MSIIR)
Table 8-39. MSIIR Field Descriptions
Bits Name Description
0–2 SRS Shared interrupt register select. Select the message shared interrupt register.
000 Message shared interrupt register 0
001 Message shared interrupt register 1
010 Message shared interrupt register 2
...
111 Message shared interrupt register 7
3–7 IBS Interrupt bit select. Select the bit to set.
00000 Set bit 31 (SH0)
00001 Set bit 30 (SH1)
00010 Set bit 29 (SH2)
...
11111 Set bit 0 (SH31)
8–31 — Reserved