Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-42 Freescale Semiconductor
8.7.2.3 Message Shared Interrupt Status Register (MSISR)
This register contains the status bits for the message shared interrupts. The status bit is set to 1 when the
corresponding message shared interrupt is active. The status bit is 0 if all the corresponding shared
interrupt sources are cleared in the message shared interrupt register (MSIR). This register is read-only.
Figure 8-32 shows the message shared interrupt status register.
Table 8-38 describes the bits of the MSISR.
8.7.2.4 Message Shared Interrupt Index Register (MSIIR)
This register provides a mechanism for setting an interrupt in the message shared interrupt registers. There
are two fields. When this register is written, one field selects the register in which an interrupt bit is to be
set and the other field selects the bit in the selected register to set. This register is write-only.
26 M5 Mask 5. Set to 1 masks interrupt generation for message shared interrupt register 5
27 M4 Mask 4. Set to 1 masks interrupt generation for message shared interrupt register 4
28 M3 Mask 3. Set to 1 masks interrupt generation for message shared interrupt register 3
29 M2 Mask 2. Set to 1 masks interrupt generation for message shared interrupt register 2
30 M1 Mask 1. Set to 1 masks interrupt generation for message shared interrupt register 1
31 M0 Mask 0. Set to 1 masks interrupt generation for message shared interrupt register 0
Offset 0xF4 Access: Read Only
0 23 24 25 26 27 28 29 30 31
R
—
S7 S6 S5 S4 S3 S2 S1 S0
W
Reset All zeros
Figure 8-32. Message Shared Interrupt Status Register (MSISR)
Table 8-38. MSISR Field Descriptions
Bits Name Description
0–23 — Reserved.
24 S7 Status 7. Set to 1 when message shared interrupt 7 is active
25 S6 Status 6. Set to 1 when message shared interrupt 6 is active
26 S5 Status 5. Set to 1 when message shared interrupt 5 is active
27 S4 Status 4. Set to 1 when message shared interrupt 4 is active
28 S3 Status 3. Set to 1 when message shared interrupt 3 is active
29 S2 Status 2. Set to 1 when message shared interrupt 2 is active
30 S1 Status 1. Set to 1 when message shared interrupt 1 is active
31 S0 Status 0. Set to 1 when message shared interrupt 0 is active
Table 8-37. MSIMR Field Descriptions (continued)
Bits Name Description