Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 8-41
Figure 8-30 shows the message shared interrupt registers.
Table 8-36 describes the bits of the MSIRs.
8.7.2.2 Message Shared Interrupt Mask Register (MSIMR)
The MSIMR contains the mask bits for the message shared interrupt register interrupts. The mask bit
corresponding to a message shared interrupt register must be clear to enable interrupt generation when the
message input region is written and a bit in the message shared interrupt register is set. This is a read-write
register.
Figure 8-31 shows the message shared interrupt mask register.
Table 8-37 describes the bits of the MSIMR.
Offset 0xC0
0xC4
0xC8
0xCC
0xD0
0xD4
0xD8
0xDC
Access: Special
0123456789101112131415
R SH31 SH30 SH29 SH28 SH27 SH26 SH25 SH24 SH23 SH22 SH21 SH20 SH19 SH18 SH17 SH16
W
Reset All zeros
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R SH15 SH14 SH13 SH12 SH11 SH10 SH9 SH8 SH7 SH6 SH5 SH4 SH3 SH2 SH1 SH0
W
Reset All zeros
Figure 8-30. Message Shared Interrupt Register (MSIRs)
Table 8-36. MSIRs Field Descriptions
Bits Name Description
31–0 SHn Message sharer n (n = 31–0) has a pending interrupt.
Offset 0xF0 Access: Read/Write
0 23 24 25 26 27 28 29 30 31
R
— M7M6M5M4M3M2M1M0
W
Reset All zeros
Figure 8-31. Message Shared Interrupt Mask Register (MSIMR)
Table 8-37. MSIMR Field Descriptions
Bits Name Description
0–23 — Reserved.
24 M7 Mask 7. Set to 1 masks interrupt generation for message shared interrupt register 7
25 M6 Mask 6. Set to 1 masks interrupt generation for message shared interrupt register 6