Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-40 Freescale Semiconductor
8.7 Message Shared Interrupts
The massage shared interrupt (MSI) registers enable the PCI Express end points to generate interrupt
requests to the local e300 CPU. Each end point can generate an interrupt and set a unique bit in one of the
eight MSIR registers. Clearing the MSIR register happens immediately after the read of its content, and
by then a new set operation can begin. MSIRn is considered active if it contains at least one bit set. Each
active non masked MSIRn register will generate an interrupt.
8.7.1 Memory Map/Register Definition
The MSI programmable register map occupies 64 bytes of memory-mapped space. The MSI registers are
32-bit wide and must be accessed in a 32-bit read or write operation. The listed addresses are offset from
the IPIC base address. Table 8-35 shows the message shared registers address map.
8.7.2 Message Shared Registers
This section contains the description of all of the message shared interrupt registers.
8.7.2.1 Message Shared Interrupt Register (MSIRs)
There are eight MSIRs indicating the interrupt sources that share the message have pending interrupts. Up
to 32 sources can share any individual message register. These registers are cleared when read. A write to
these registers has no effect.
Table 8-35. Message Shared Registers Address Map
Offset Register Access Reset Section/page
0xC0 MSIR0—Message shared interrupt register 0 Special 0x0000_0000 8.7.2.1/8-40
0xC4 MSIR1—Message shared interrupt register 1 Special 0x0000_0000 8.7.2.1/8-40
0xC8 MSIR2—Message shared interrupt register 2 Special 0x0000_0000 8.7.2.1/8-40
0xCC MSIR3—Message shared interrupt register 3 Special 0x0000_0000 8.7.2.1/8-40
0xD0 MSIR4—Message shared interrupt register 4 Special 0x0000_0000 8.7.2.1/8-40
0xD4 MSIR5—Message shared interrupt register 5 Special 0x0000_0000 8.7.2.1/8-40
0xD8 MSIR6—Message shared interrupt register 6 Special 0x0000_0000 8.7.2.1/8-40
0xDC MSIR7—Message shared interrupt register 7 Special 0x0000_0000 8.7.2.1/8-40
0xE0–0xEC Reserved — — —
0xF0 MSIMR—Message shared interrupt mask register R/W 0x0000_0000 8.7.2.2/8-41
0xF4 MSISR—Message shared interrupt status register R 0x0000_0000 8.7.2.3/8-42
0xF8 MSIIR—Message shared interrupt index register W 0x0000_0000 8.7.2.4/8-42
0xFC Reserved — — —