Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 8-39
Figure 8-29 shows an example of how the masking occurs using a DDR block.
Figure 8-29. DDR Interrupt Request Masking
8.6.8 Interrupt Vector Generation and Calculation
Pending unmasked interrupts are presented to the core in order of priority according to Table 8-34. The
interrupt vector that allows the core to locate the interrupt service routine is made available to the core by
interrupt handler software reading SIVCR. The interrupt controller passes an interrupt vector
corresponding to the highest-priority, unmasked, pending interrupt in response to a read of SIVCR.
Table 8-5 lists the encodings for the seven low-order bits of the interrupt vector.
8.6.9 Machine Check Interrupts
The IPIC supports the non-maskable machine check interrupts. When an error interrupt signal is received,
the interrupt controller indicates the source by setting the corresponding SERSR bit. These sources are
listed in Table 8-23.
DDR EVENT
DDR MASK
XX Input (or
SIPNR
Mask
Bit
SIMSR
(Other Unmasked Requests)
Request to
the core
Mask
Bit
Event
Bit
XX Event Bits)