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Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-38 Freescale Semiconductor
8.6.7 Masking Interrupt Sources
By programming the system interrupt mask registers, SIMSRx and SEMSR, the user can mask interrupt
requests to the core. Each SIMSRx and SEMSR bit corresponds to an interrupt source. To enable an
interrupt, set the corresponding SIMSR or SEMSR bit. When a masked interrupt source has a pending
interrupt request, the corresponding SIPNRx or SEMSR bit is set, even though the interrupt is not
generated to the core. The user can mask all interrupt sources to implement a polling interrupt servicing
scheme.
When an interrupt source has multiple interrupting events, the user can individually mask these events by
programming a mask register within that particular block. Table 8-34 shows the interrupt sources that have
multiple interrupting events.
124 DMAC Err
125 SYSC7 (Spread)
126 SYSD7 (Spread)
127 Reserved
128 Reserved
Table 8-34. Interrupt Source Priority Levels (continued)
Priority Interrupt Source Description