Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-34 Freescale Semiconductor
• Spread.
In the spread scheme, priorities are spread over the table so other sources can have lower interrupt
latencies. This scheme is also programmed but cannot be changed dynamically.
8.6.5 Highest Priority Interrupt
In addition to the group relative priority option, SICFR[HPI] can be used to specify one interrupt source
as having the highest priority. This interrupt remains within the same interrupt level as the other interrupt
controller interrupts, but is serviced before any other interrupt in Table 8-34.
If the highest priority feature is not used, the IPIC selects the interrupt request in MIXA0 to be the highest
priority interrupt and the standard interrupt priority order is used from Table 8-34. SICFR[HPI] can be
updated dynamically to allow the user to change a normally low priority source into a high priority-source
for a period as needed.
8.6.6 Interrupt Source Priorities
Each of the IPIC’s internal and external interrupt sources can independently assert one interrupt request to
the core. Table 8-34 shows the prioritization of these interrupt sources. As described in previous sections,
flexibility exists in the relative ordering of the interrupts, but, in general, relative priorities are as shown.
A single interrupt priority number is associated with each table entry.
Table 8-34. Interrupt Source Priority Levels
Priority Interrupt Source Description
1 Highest
2 MIXA0 (Grouped/Spread)
3 MIXA1 (Grouped)
4 MIXA2 (Grouped)
5 MIXA3 (Grouped)
6 MIXB0 (Spread)
7 SYSB0 (Grouped)
8 SYSB1 (Grouped)
9 SYSB2 (Grouped)
10 SYSB3 (Grouped)
11 MIXA1 (Spread)
12 SYSB4 (Grouped)
13 SYSB5 (Grouped)
14 SYSB6 (Grouped)
15 SYSB7 (Grouped)
16 MIXB0 (Grouped)
17 MIXB1 (Grouped)
18 MIXB2 (Grouped)
19 MIXB3 (Grouped)