Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 8-33
All interrupt sources are prioritized and bits are set in the system interrupt pending register (SIPNR,
SEPNR) as interrupts occur regardless of whether they are masked in the IPIC. The prioritization of the
interrupt sources is flexible within the following groups:
• The relative priority of the eTSEC1 Tx, eTSEC1 Rx, eTSEC1 Err, eTSEC2 Tx, eTSEC2 Rx,
eTSEC2 Err, and USB DR internal interrupt signals can be modified.
• The relative priority of the eSDHC internal interrupt signal can be modified.
• The relative priority of the PCI Express, DMAC, and MSIR1 internal interrupts can be modified.
• The relative priority of the UART1, UART2, eTSEC1 1588, eTSEC2 1588, I2C1, I2C2, and SPI
internal interrupt signals can be modified.
• The relative priority of the RTC SEC, PIT, and MSIR0 internal interrupts along with IRQ0, IRQ1,
IRQ2, and IRQ3 external interrupts can be modified.
• The relative priority of the RTC ALR and SBA internal interrupts can be modified.
• One interrupt source can be assigned to be the programmable highest priority.
The SIVCR is updated with a 7-bit vector corresponding to the sub-block with the highest current priority.
8.6.3 Internal Interrupts Group Relative Priority
The relative priority in each internal group is programmable and can be changed dynamically. The group
priorities are programmed in the IPIC internal interrupt priority registers (SIPRRx) and can be changed
dynamically to implement a rotating priority.
In addition, the grouping of the locations of the interrupt entries has the following two options:
• Grouped.
In the group scheme, all interrupts are grouped together at the top of Table 8-34, ahead of most
other interrupt sources. This scheme is ideal for applications where all interrupt sources function
at a very high data rate and interrupt latency is very important.
• Spread.
In the spread scheme, priorities are spread over Table 8-34 so other sources can have lower
interrupt latencies. This scheme is also programmed but cannot be changed dynamically.
8.6.4 Mixed Interrupts Group Relative Priority
The relative priority between up to four internal and four external interrupts in each group is programmable
and can be changed dynamically. The group priorities are programmed in the IPIC mixed interrupt priority
registers (SMPRRx) and can be changed dynamically to implement a rotating priority.
In addition, the grouping of the locations of the mixed interrupt entries has the following two options:
• Grouped.
In the group scheme, all interrupts are grouped together at the top of the priority table, ahead of
most other interrupt sources. For more information, see Table 8-34. This scheme is ideal for
applications where all interrupt sources function at a very high data rate and interrupt latency is
very important.