Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-32 Freescale Semiconductor
8.6.2 Interrupt Configuration
Figure 8-28 shows the interrupt configuration.
Figure 8-28. Interrupt Structure
The interrupt controller allows masking of each interrupt source. When an unmasked interrupt source is
pending in the SIPNR register, the interrupt controller sends an interrupt request to the core. When an
interrupt is taken, the interrupt mask bit in the machine state register is cleared to disable further interrupt
requests to the e300 core until software can handle them.
smi
e300
DMA
GTM1
I2C
System Interrupts
DUART
eTSEC 1
LB MEMC
PIT
RTC
DDR MEMC
4
4
int
cint
mcp
WDT
System Bus Arbiter
mcp
mcp
ext mcp
MCP Interrupts
(Internal and External)
ext int
(Internal and External)
Interrupt
Controller
MPC8308
4
2
SPI
(SBA)
System Bus Arbiter
(SBA)
Core
MCP_OUT
IRQ[0], IRQ[1]
IRQ[0]
2
4
GPIO
PCI Express
MSIR
2
eSDHC
IRQ[2], IRQ[3]
2
eTSEC 2
4
USB 2.0
8