Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
xxx Freescale Semiconductor
Figures
Figure
Number Title
Page
Number
14-69 PCI Express Uncorrectable Error Severity Register........................................................... 14-55
14-70 PCI Express Correctable Error Status Register................................................................... 14-56
14-71 PCI Express Correctable Error Mask Register ................................................................... 14-57
14-72 PCI Express Advanced Error Capabilities and Control Register........................................ 14-58
14-73 PCI Express Header Log Register ...................................................................................... 14-59
14-74 PCI Express Root Error Command Register....................................................................... 14-60
14-75 PCI Express Root Error Status Register.............................................................................. 14-60
14-76 PCI Express Error Source Identification Register .............................................................. 14-61
14-77 PCI Express LTSSM State Status Register (PEX_LTSSM_STAT) .................................... 14-62
14-78 PCI Express N_FTS Control Register ................................................................................ 14-64
14-79 PCI Express ACK Replay Timeout Register ...................................................................... 14-64
14-80 PCI Express Core Clock Ratio Register (PEX_GCLK_RATIO)........................................ 14-66
14-81 PCI Express Power Management Timer Register (PEX_PM_TIMER) ............................. 14-66
14-82 PCI Express PME Time-Out Register (PEX_PME_TIMEOUT) ....................................... 14-67
14-83 PCI Express ASPM Request Timer Register...................................................................... 14-67
14-84 PCI Express Subsystem Vendor ID Update Register (PEX_SSVID_UPDATE)................ 14-68
14-85 PCI Express Device Capabilities Update Register ............................................................. 14-69
14-86 PCI Express Link Capabilities Update Register ................................................................. 14-70
14-87 PCI Express Slot Capabilities Update Register .................................................................. 14-71
14-88 PCI Express Configuration Ready Register (PEX_CFG_READY)................................... 14-72
14-89 PCI Express BAR Size Low Configuration Register (PEX_BAR_SIZEL) ....................... 14-73
14-90 PCI Express BAR Select Configuration Register (PEX_BAR_SEL) ................................ 14-73
14-91 PCI Express BAR Prefetch Configuration Register (PEX_BAR_PF)................................ 14-74
14-92 PCI Express PME_To_Ack Timeout Register (PEX_PME_TO_ACK_TOR)................... 14-75
14-93 PME_To_Ack Status Register (PEX_PME_TO_ACK_SR)............................................... 14-75
14-94 PCI Express PCI Interrupt Mask Register (PEX_SS_INTR_MASK)................................ 14-76
14-95 PCI Express CSB Bridge Control Register (PEX_CSB_CTRL)........................................ 14-78
14-96 PCI Express DMA Descriptor Timer Register (PEX_DMA_DSTMR) ............................. 14-79
14-97 PCI Express CSB Bridge Status Register (PEX_CSB_STAT) ........................................... 14-79
14-98 PCI Express Outbound PIO Control Register (PEX_CSB_OBCTRL) .............................. 14-80
14-99 PCI Express Outbound PIO Status Register (PEX_CSB_OBSTAT).................................. 14-81
14-100 PCI Express Inbound PIO Control Register (PEX_CSB_IBCTRL) .................................. 14-82
14-101 PCI Express Inbound PIO Status Register (PEX_CSB_IBSTAT)...................................... 14-83
14-102 PCI Express Write DMA Control Register (PEX_WDMA_CTRL) .................................. 14-84
14-103 PCI Express Write DMA First Address Register (PEX_WDMA_ADDR)........................ 14-84
14-104 PCI Express Write DMA Status Register (PEX_WDMA_STAT)...................................... 14-85
14-105 PCI Express Read DMA Control Register (PEX_RDMA_CTRL) .................................... 14-86
14-106 PCI Express Read DMA First Address Register (PEX_RDMA_ADDR).......................... 14-86
14-107 PCI Express Read DMA Status Register (PEX_RDMA_STAT)........................................ 14-87
14-108 PCI Express Outbound Mailbox Control Register (PEX_OMBCR).................................. 14-88
14-109 MPCI Express Outbound Mailbox Data Register (PEX_OMBDR)................................... 14-88