Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 8-29
8.5.20 System External Interrupt Force Register (SEFCR)
Each implemented bit in SEFCR, shown in Figure 8-24, corresponds to an external interrupt source. When
a bit is set, the interrupt controller generates the corresponding external interrupt (sets the corresponding
SEPNR bit). SEFCR can be read by the user at any time.
Table 8-30 defines the bit fields of SEFCR.
8.5.21 System Error Force Register (SERFR)
Each bit in the system error force register (SERFR), shown in Figure 8-25, corresponds to an external MCP
source. When a bit is set, the interrupt controller generates the corresponding MCP interrupt (sets the
corresponding SERSR bit). The SERFR can be read by the user at any time.
Offset 0x58 Access: Read/write
0 1234 15
R
IRQ0
1
IRQ1 IRQ2 IRQ3 —
W
Reset All zeros
16 31
R
—
W
Reset All zeros
1
This bit is valid only if IRQ0 is configured as an external maskable interrupt (SEMSR[SIRQ0] = 0)
Figure 8-24. System External Interrupt Force Register (SEFCR)
Table 8-30. SEFCR Field Descriptions
Bits Name Description
0, 1,
2, 3
IRQn Each bit corresponds to an external interrupt source. The user forces an interrupt by setting the SEFCR bit.
Note: SEFCR bit positions are not affected by their relative priority.
4–31 — Write ignored, read = 0
Offset 0x5C Access: Read/write
0 31
R
INTn (Implemented bits are listed in Tabl e 8- 23.)
W
Reset All zeros
Figure 8-25. System Error Status Register (SERFR)