Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-28 Freescale Semiconductor
Table 8-28 defines the bit fields of SIFCR_H.
SIFCR_L is shown in Figure 8-23.
Table 8-29 defines the bit fields of SIFCR_L.
Table 8-28. SIFCR_H Field Descriptions
Bits Name Description
0–31 INTn Each implemented bit, listed in Ta ble 8 -7 , corresponds to an internal interrupt source. The user forces an
interrupt by setting the corresponding SIFCRx bit. SIFCRn bit positions are not changed according to their
relative priority.
Writes to unimplemented (reserved) bits are ignored; read = 0
Offset 0x54 Access: Read/write
0 31
R
INTn (Implemented bits are listed in Ta bl e 8-9 ).
W
Reset All zeros
Figure 8-23. System Internal Interrupt Force Register (SIFCR_L)
Table 8-29. SIFCR_L Field Descriptions
Bits Name Description
0–31 INTn Each implemented bit, listed in Ta ble 8 -9 , corresponds to an internal interrupt source. The user forces an
interrupt by setting the corresponding SIFCRx bit. SIFCRx bit positions are not changed according to their
relative priority.
Writes to unimplemented (reserved) bits are ignored; read = 0