Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 8-27
pin. The active high signals assert an interrupt request upon either a low-to-high change or assertion (high
state) on the pin. See Section 8.5.14, “System External Interrupt Control Register (SECNR),” on page 8-23
for more details.
NOTE
Note that the IRQn signals are overbarred although the SEPCR could be
programmed to accept active high signals. The overbar should be ignored in
this case.
Table 8-27 defines the bit fields of SEPCR.
8.5.19 System Internal Interrupt Force Registers (SIFCR_H and SIFCR_L)
Each implemented bit SIFCR_H and SIFCR_L, shown in Figure 8-22 and Figure 8-23, corresponds to an
internal interrupt source. When a bit is set, the interrupt controller generates the corresponding interrupt
(sets the corresponding SIPNR bit). The SIFCR can be read by the user at any time.
Offset 0x4C Access: Read/write
01234 15
R
EIP0 EIP1 EIP2 EIP3 —
W
Reset All zeros
16 31
R
—
W
Reset All zeros
Figure 8-21. System External Interrupt Polarity Control Register (SEPCR)
Table 8-27. SEPCR Field Descriptions
Bits Name Description
0–3 EIPx Each bit defines the active state for the IRQn interrupt signals.
0 Active Low.
1 Active High.
4–31 — Write ignored, read = 0
Offset 0x50 Access: Read/write
0 31
R
INTn (Implemented bits are listed in Tabl e 8- 7.)
W
Reset All zeros
Figure 8-22. System Internal Interrupt Force Register (SIFCR_H)