Information

Integrated Programmable Interrupt Controller (IPIC)

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

8-26 Freescale Semiconductor

Table 8-25 defines the bit fields of SERMR.

8.5.17 System Error Control Register (SERCR)

SERCR, shown in Figure 8-20, defines the control bits that route MCP requests in core disable mode to

MCP_OUT

Table 8-26 defines the bit fields of SERCR.

8.5.18 System External interrupt Polarity Control Register (SEPCR)

SEPCR, shown in Figure 8-21, defines the polarity for each one of the external IRQn interrupt signals and

determines whether the corresponding IRQ

n signal is treated as active low or active high signal. The active

low signals will assert an interrupt request upon either a high-to-low change or assertion (low state) on the

Offset 0x44 Access: Read/write

0 31

INTn (Implemented bits are listed in Table 8 -23.)

Reset Implemented bits reset to ones; unimplemented (reserved) bits reset to zeros.

Figure 8-19. System Error Mask Register (SERMR)

Table 8-25. SERMR Field Descriptions

Bits Name Description

0–31 INTn Each implemented SERMR bit, listed in Ta bl e 8- 23 , corresponds to an external and an internal MCP source.

The user masks an MCP by clearing and enables an interrupt by setting the corresponding SERMR bit.

When a masked MCP occurs, the corresponding SERSR bit is set, regardless of the setting of the SERMR

bit although no MCP request is passed to the core. The SERMR can be read by the user at any time.

Writes to unimplemented (reserved) bits are ignored; read = 0

Offset 0x48 Access: Read/write

0 30 31

—MCPR

Reset All zeros

Figure 8-20. System Error Control Register (SERCR)

Table 8-26. SERCR Field Descriptions

Bits Name Description

0–30 — Write ignored, read = 0

31 MCPR MCP route. Route MCP request to M

CP_OUT.

0 MCP is not available at MCP_OUT

1 MCP routed to MCP_OUT.