Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 8-25
8.5.15 System Error Status Register (SERSR)
The bits in the SERSR, shown in Figure 8-18, correspond to the external and internal non-maskable error
source machine check (mcp) conditions listed in Table 8-23. When an error interrupt signal is received, the
interrupt controller sets the corresponding SERSR bit.
Table 8-23 lists the implemented SERSR bits. Note that these field assignments are valid for SERMR and
SERFR.
Table 8-24 defines the bit fields of SERSR.
8.5.16 System Error Mask Register (SERMR)
Each implemented bit in SERMR, shown in Figure 8-19, corresponds to an external and an internal mcp
source (MCP). The user masks an MCP by clearing and enables an interrupt by setting the corresponding
SERMR bit. When a masked MCP occurs, the corresponding SERSR bit is set, regardless of the setting of
the corresponding SERMR bit although no MCP request is passed to the core in this case. The SERMR
can be read by the user at any time.
Offset 0x40 Access: Read/write
0 31
R
INTn (Implemented bits are listed in Tabl e 8- 23)
W
Reset All zeros
Figure 8-18. System Error Status Register (SERSR)
Table 8-23. SERSR/SERMR/SERFR Bit Assignments
Bits Field
0IRQ0
1
1
This bit is valid only if the IRQ0 signal is
configured as an external MCP interrupt
(SEMSR[SIRQ0] = 1)
1WDT
2
SBA
3–31 —
Table 8-24. SERSR Field Descriptions
Bits Name Description
0–31 INTn Each implemented bit in the SERSR, listed in Ta ble 8-23, corresponds to an external and an internal error source
(mcp). When an error interrupt signal is received, the interrupt controller sets the corresponding SERSR bit.
SERSR bits are cleared by writing ones to them. Unmasked event register bits should be cleared before clearing
SERSR bits. Because the user can only clear bits in this register, writing zeros to this register has no effect.
SERSR bits are cleared by power-on reset. Subsequent soft and hard resets do not affect SERSR bit states.
For unimplemented bits (listed as reserved in Tabl e 8- 23), writes are ignored, read = 0