Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-24 Freescale Semiconductor
Table 8-22 defines the bit fields of SECNR.
Offset 0x3C Access: Read/write
0 1 2 3 4 7 8 9 10 11 12 15
R
MIXB0T MIXB1T — MIXA0T MIXA1T —
W
Reset All zeros
16 17 18 19 20 31
R
EDI0 EDI1 EDI2 EDI3 —
W
Reset All zeros
Figure 8-17. System External Interrupt Control Register (SECNR)
Table 8-22. SECNR Field Descriptions
Bits Name Description
0–1 MIXB0T MIXB0 priority position IPIC output interrupt type. Defines which type of the IPIC output interrupt signal (int
,
cint, or smi) asserts its request to the core in the MIXB0 priority position. These bits can be changed
dynamically. The definition of MIXB0T is as follows:
00 int
request is asserted to the core for MIXB0.
01 smi request is asserted to the core for MIXB0.
10 cint request is asserted to the core for MIXB0.
11 Reserved
2–3 MIXB1T Same as MIXB0T, but for MIXB1T.
4–7 — Write ignored, read = 0
8–9 MIXA0T MIXA0 priority position IPIC output interrupt Type. Defines which type of the IPIC output interrupt signal (int
,
cint, or smi) asserts its request to the core in the MIXA0 priority position. These bits can be changed
dynamically. The definition of MIXA0T is as follows:
00 int
request is asserted to the core for MIXA0.
01 smi
request is asserted to the core for MIXA0.
10 cint
request is asserted to the core for MIXA0.
11 Reserved
10–11 MIXA1T Same as MIXA0T, but for MIXA1T.
12–15 — Write ignored, read = 0
16–19 EDIx Each bit defines the edge detect mode for the external IRQ
n interrupt signals, determines whether the
corresponding IRQn signal asserts an interrupt request upon either a high-to-low (high assertion for active
high polarity) change or low assertion (high assertion for active high polarity) on the pin. The corresponding
IRQ
n signal asserts an interrupt request as follows:
0 Low assertion (high assertion for active high polarity) on IRQn generates an interrupt request (level
sensitive).
1 High-to-low (low-to-high for active high polarity) change on IRQ
n generates an interrupt request (edge
sensitive).
20–31 — Write ignored, read = 0