Information
Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 8-23
Table 8-21 defines the bit fields of SEMSR.
8.5.14 System External Interrupt Control Register (SECNR)
SECNR, shown in Figure 8-17, defines the edge detect mode for external IRQn interrupt signals and
determines whether the corresponding IRQ
n signal asserts an interrupt request upon either a high-to-low
change or assertion on the pin. It also defines the IPIC output interrupt type (int, cint, or smi) in the
MIXA0–MIXA1 and MIXB0–MIXB1 priority positions.
Note that in core disabled mode of operation the user should use the int
output interrupt type (should not
use cint or smi output interrupt types) in order to read an updated SIVCR.
Offset 0x38 Access: Read/write
0 1234 15
R
IRQ0
1
IRQ1 IRQ2 IRQ3 —
W
Reset All Zeros
16 17 31
R
SIRQ0 —
W
Reset All zeros
1
This bit is valid only if the IRQ0 signal is configured as an external maskable interrupt (SEMSR[SIRQ0] = 0)
Figure 8-16. System External Interrupt Mask Register (SEMSR)
Table 8-21. SEMSR Field Descriptions
Bits Name Description
0, 1,
2, 3
— Each bit corresponds to an external interrupt source. The user masks an interrupt by clearing the SEMSR bit.
An interrupt can be enabled by setting the corresponding SEMSR bit.
SEMSR can be read by the user at any time.
Note:
• SEMSR bit positions are not affected by their relative priority.
• The user can clear pending register bits that were set by multiple interrupt events only by clearing all
unmasked events in the corresponding event register.
• If an SEMSR bit is masked at the same time that the corresponding SEPNR bit causes an interrupt request
to the core, the error vector is issued (if no other interrupts pending). Thus, the user must always include an
error vector routine, even if it contains only an rfi instruction. The error vector cannot be masked.
4–15 — Write ignored, read = 0
16 SIRQ0 Steer IRQ0.
0 IRQ0 is used as external interrupt request
1 IRQ0 is used as external MCP request
17–31 — Write ignored, read = 0