Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-22 Freescale Semiconductor
8.5.12 System Mixed Interrupt Group B Priority Register (SMPRR_B)
SMPRR_B, shown in Figure 8-15, defines the priority among the sources listed in Table 8-20.
Table 8-20 defines the bit fields of SMPRR_B.
8.5.13 System External Interrupt Mask Register (SEMSR)
Each bit in the system external interrupt mask register (SEMSR), shown in Figure 8-13, corresponds to an
external interrupt source. The user masks an interrupt by clearing the corresponding SEMSR bit. An
interrupt is unmasked (enabled) by setting the corresponding SEMSR bit.
When an external interrupt request occurs, the corresponding SEPNR bit is set regardless of the setting of
the corresponding SEMSR bit. However, if the corresponding SEMSR bit is cleared, no interrupt request
is passed to the core.
When simultaneously an SEMSR bit is cleared by the user and an interrupt source requests an interrupt
service, the request stops. If the user sets the SEMSR bit later, a previously pending interrupt request is
processed by the core according to its assigned priority. SEMSR can be read by the user at any time.
Offset 0x34 Access: Read/write
0 2 3 5 6 8 9 1112 1516 1819 2122 2425 2728 31
R
MIXB0P MIXB1P MIXB2P MIXB3P — MIXB4P MIXB5P MIXB6P MIXB7P —
W
Reset00000101001100001001011101110000
Figure 8-15. System Mixed Interrupt Group B Priority Register (SMPRR_B)
Table 8-20. SMPRR_B Field Descriptions
Bits Name Description
0–2, 3–11, 16–27 MIXBnPMIXBn priority order. Defines which interrupt source asserts its request in the MIXBn priority
position. The user must not program the same code to more than one priority position (0–7).
These bits can be changed dynamically. The definition of MIXBnP is as follows:
000 RTC ALR asserts its request to the MIXBn position.
001 Reserved
010 SBA asserts its request to the MIXBn position.
011–111 Reserved
12–15, 28–31 — Write ignored, read = 0