Information
Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 8-21
Table 8-18 defines the bit fields of SEPNR.
8.5.11 System Mixed Interrupt Group A Priority Register (SMPRR_A)
The SMPRR_A, shown in Figure 8-14, defines the priority among the sources listed in Table 8-19.
Table 8-19 defines the bit fields of SMPRR_A.
Table 8-18. SEPNR Field Descriptions
Bits Name Description
0, 1,
2, 3
IRQn Each bit corresponds to an external interrupt source. When an external interrupt is received, the interrupt
controller sets the corresponding SEPNR bit.
When a pending interrupt is handled, the user must clear the corresponding SEPNR bit. For level triggered
cases, the software needs to cause the IRQn
to negate which automatically clears the bit in SEPNR. For
edge-triggered cases, the software needs to clear the corresponding bit in SEPNR.
SEPNR bits are cleared by writing ones to them. Because the user can only clear bits in this register, writing
zeros to this register has no effect.
Note that the SEPNR bit positions are not changed according to their relative priority.
4-31 — Write ignored, read = 0
Offset 0x30 Access: Read/write
0 2 3 5 6 8 9 1112 1516 1819 2122 2425 2728 31
R
MIXA0P MIXA1P MIXA2P MIXA3P — MIXA4P MIXA5P MIXA6P MIXA7P —
W
Reset00000101001100001001011101110000
Figure 8-14. System Mixed Interrupt Group A Priority Register (SMPRR_A)
Table 8-19. SMPRR_A Field Descriptions
Bits Name Description
0–2 MIXA0P MIXA0 priority order. Defines which interrupt source asserts its request in the MIXA0 priority
position. The user must not program the same code to more than one priority position (0–7).
These bits can be changed dynamically. The definition of MIXA0P is as follows:
000 RTC SEC asserts its request to the MIXA0 position.
001 PIT asserts its request to the MIXA0 position.
010 Reserved
011 MSIR0 asserts its request to the MIXA0 position.
100 IRQ0 asserts its request to the MIXA0 position. This field for MIXA0 position is valid
(must not be ignored) if IRQ0
signal configured as an external maskable interrupt
(SEMSR[SIRQ0] = 0).
101 IRQ1 asserts its request to the MIXA0 position.
110 IRQ2 asserts its request to the MIXA0 position.
111 IRQ3 asserts its request to the MIXA0 position.
3–11, 16–27 MIXA1P–MIXA7P Same as MIXA0P, but for MIXA1P–MIXA7P.
12–15,
28–31
— Write ignored, read = 0