Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-20 Freescale Semiconductor
8.5.10 System External Interrupt Pending Register (SEPNR)
Each bit in the SEPNR, shown in Figure 8-13, corresponds to an external interrupt source. When an
interrupt is received, the interrupt controller sets the corresponding SEPNR bit.
24–25 SYSA0T SYSA0 priority position IPIC output interrupt type. Defines which type of the IPIC output interrupt signal (int,
smi
, or cint) asserts its request to the core in the SYSA0 priority position. These bits cannot be changed
dynamically. (If software really wants to change it, it has to make sure the corresponding interrupt source is
masked or it does not happen during the change).
The definition of SYSA0T is as follows:
00 int
request is asserted to the core for SYSA0.
01 smi
request is asserted to the core for SYSA0.
10 cint request is asserted to the core for SYSA0.
11 Reserved.
26–27 SYSA1T Same as SYSA0T, but for SYSA1T
28–31 — Write ignored, read = 0
Offset 0x2C Access: Read/write
01234 15
R
IRQ0
1
IRQ1 IRQ2 IRQ3 —
W
Reset The reset values of implemented bits reflect the values of the external IRQ signals. Reserved bits are zeros.
2
16 31
R
—
W
Reset All zeros
1
This bit is valid only if the IRQ0 signal is configured as an external maskable interrupt (SEMSR[SIRQ0] = 0)
2
The user should drive all IRQ inputs to an inactive state prior to reset negation
Figure 8-13. System External Interrupt Pending Register (SEPNR)
Table 8-17. SICNR Field Descriptions (continued)
Bits Name Description