Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-18 Freescale Semiconductor
Table 8-15 defines the bit fields of SIMSR_H.
Figure 8-11 shows SIMSR_L.
Table 8-16 defines the bit fields of SIMSR_L.
8.5.9 System Internal Interrupt Control Register (SICNR)
SICNR, shown in Figure 8-12, defines the IPIC output interrupt type (int, cint, or smi) in the
SYSA0–SYSA1, SYSB0–SYSB1, SYSC0–SYSC1, and SYSD0–SYSD1 priority positions. All other
priority positions assert int
to the core.
Table 8-15. SIMSR_H Field Descriptions
Bits Name Description
0–31 INTn Each implemented bit (listed in Tabl e 8- 7) corresponds to an external interrupt source. The user masks an
interrupt by clearing the corresponding SIMSR bit. An interrupt is unmasked (enable) by setting the
corresponding SIMSR bit. The SIMSR can be read by the user at any time.
Note:
• SIMSR bit positions do not change according to their relative priority.
• The user can clear pending register bits that were set by multiple interrupt events only by clearing all
unmasked events in the corresponding event register.
• If an SIMSR bit is masked at the same time that the corresponding SIPNR bit causes an interrupt request to
the core, the error vector is issued (if no other interrupts are pending). Thus, the user should always include
an error vector routine, even if it contains only an rfi instruction. The error vector cannot be masked.
Unimplemented bits, shown as reserved in Table 8- 7, are ignored on writes; read = 0.
Offset 0x24 Access: Read/write
0 31
R
INTn (Implemented bits are listed in Ta bl e 8-9 .)
W
Reset All zeros
Figure 8-11. System Internal Interrupt Mask Register (SIMSR_L)
Table 8-16. SIMSR_L Field Descriptions
Bits Name Description
0–31 INTn Each implemented bit (listed in Table 8 -9) corresponds to an external interrupt source. The user masks an
interrupt by clearing the corresponding SIMSR bit. An interrupt is unmasked (enabled) by setting the
corresponding SIMSR bit. The SIMSR can be read by the user at any time.
Note:
• SIMSR bit positions are not changed according to their relative priority.
• The user can clear pending register bits that were set by multiple interrupt events only by clearing all unmasked
events in the corresponding event register.
• If an SIMSR bit is masked at the same time that the corresponding SIPNR bit causes an interrupt request to
the core, the error vector is issued (if no other interrupts are pending). Thus, the user should always include
an error
Unimplemented bits, shown as reserved in Figure 8-11, are ignored on writes; read = 0.