Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 8-17
Table 8-14 defines the bit fields of SIPRR_D.
8.5.8 System Internal Interrupt Mask Register (SIMSR_H and SIMSR_L)
Each implemented bit in SIMSR_H and SIMSR_L, shown in Figure 8-10 and Figure 8-11, corresponds to
an internal interrupt source. The user masks an interrupt by clearing the corresponding SIMSR bit. When
an interrupt request occurs, the corresponding SIPNR bit is set, regardless of the SIMSR bit. However, if
the corresponding SIMSR bit is cleared, no interrupt request is passed to the core.
When simultaneously an SIMSR bit is cleared by the user and corresponding interrupt source requests an
interrupt service, the request stops. If the user sets the SIMSR bit later, the core processes any pending
corresponding interrupt requests according to its priority.
Table 8-14. SIPRR_D Field Descriptions
Bits Name Description
0–2 SYSD0P SYSD0 priority order. Defines which interrupt source asserts its request in the
SYSD0 priority position. The user should not program the same code to more than
one priority position (0–7). These bits can be changed dynamically. SYSD0P is
defined as follows:
000 UART1 asserts its request in the SYSD0 position.
001 UART2 asserts its request in the SYSD0 position.
010 Reserved
011 eTSEC1 1588 asserts its request in the SYSD0 position.
100 eTSEC2 1588 asserts its request in the SYSD0 position.
101 I2C1 asserts its request in the SYSD0 position.
110 I2C2 asserts its request in the SYSD0 position.
111 SPI asserts its request in the SYSD0 position.
3–11, 16–27 SYSD1P–SYSD7P Same as SYSD0P, but for SYSD1P–SYSD7P.
12–15, 28–31 — Write ignored, read = 0
Offset 0x20 Access: Read/write
0 31
R
INTn (Implemented bits are listed in Tabl e 8- 7.)
W
Reset All zeros
Figure 8-10. System Internal Interrupt Mask Register (SIMSR_H)