Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-16 Freescale Semiconductor
8.5.6 System Internal Interrupt Group C Priority Register (SIPRR_C)
The system internal interrupt group C priority register (SIPRR_C), shown in Figure 8-8, defines the
priority between internal interrupt signals.
For more information about interrupt priorities, see Section 8.6.3, “Internal Interrupts Group Relative
Priority.”
Table 8-13 defines the bit fields of SIPRR_C.
8.5.7 System Internal Interrupt Group D Priority Register (SIPRR_D)
SIPRR_D, shown in Figure 8-9, defines the priority among the interrupt sources listed in Table 8-14.
Offset 0x18 Access: Read/write
0 2 3 5 6 8 9 1112 1516 1819 2122 2425 2728 31
R
SYSC0P SYSC1P SYSC2P SYSC3P — SYSC4P SYSC5P SYSC6P SYSC7P —
W
Reset00000101001100001001011101110000
Figure 8-8. System Internal Interrupt Group C Priority Register (SIPRR_C)
Table 8-13. SIPRR_C Field Descriptions
Bits Name Description
0–2 SYSC0P SYSC0 priority order.Defines which interrupt source asserts its request in the SYSC0
priority position. The user should not program the same code to more than one priority
position (0–7). These bits can be changed dynamically. The definition of SYSC0P is
shown as follows:
000 PEX1 CNT asserts its request in the SYSC0 position.
001 Reserved
010 DMAC asserts its request in the SYSC0 position.
011 MSIR1 asserts its request in the SYSC0 position
100–111 Reserved
3–11, 16–27 SYSC1P–SYSC7P Same as SYSC0P, but for SYSC1P–SYSC7P.
12–15, 28–31 — Write ignored, read = 0
Offset 0x1C Access: Read/write
0 2 3 5 6 8 9 1112 1516 1819 2122 2425 2728 31
R
SYSD0P SYSD1P SYSD2P SYSD3P — SYSD4P SYSD5P SYSD6P SYSD7P —
W
Reset00000101001100001001011101110000
Figure 8-9. System Internal Interrupt Group D Priority Register (SIPRR_D)