Information
Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 8-15
Table 8-11 defines the bit fields of SIPRR_A.
8.5.5 System Internal Interrupt Group B Priority Register (SIPRR_B)
The system internal interrupt group B priority register (SIPRR_B), shown in Figure 8-7, defines the
priority between internal interrupt signals.
For more information, see Section 8.6.3, “Internal Interrupts Group Relative Priority.”
Table 8-12 defines the bit fields of SIPRR_B.
Table 8-11. SIPRR_A Field Descriptions
Bits Name Description
0–2 SYSA0P SYSA0 priority order. Defines which interrupt source asserts its request in the SYSA0
priority position. The user should not program the same code to multiple priority positions
(0–7). These bits can be changed dynamically. The definition of SYSA0P is as follows:
000 TSEC1 Tx asserts its request in the SYSA0 position.
001 TSEC1 Rx asserts its request in the SYSA0 position.
010 TSEC1 Err asserts its request in the SYSA0 position.
011 TSEC2 Tx asserts its request in the SYSA0 position.
100 TSEC2 Rx asserts its request in the SYSA0 position.
101 TSEC2 Err asserts its request in the SYSA0 position.
110 USB DR asserts its request in the SYSA0 position.
111 Reserved
3–11, 16–27 SYSA1P–SYSA7P Same as SYSA0P, but for SYSA1P–SYSA7P.
12–15, 28–31 — Write ignored, read = 0
Offset 0x14 Access: Read/write
0 2 3 5 6 8 9 1112 1516 1819 2122 2425 2728 31
R
SYSB0P SYSB1P SYSB2P SYSB3P — SYSB4P SYSB5P SYSB6P SYSB7P —
W
Reset00000101001100001001011101110000
Figure 8-7. System Internal Interrupt Group B Priority Register (SIPRR_B)
Table 8-12. SIPRR_B Field Descriptions
Bits Name Description
0–2 SYSB0P SYSB0 Priority order.Defines which interrupt source asserts its request in the SYSB0
priority position. The user should not program the same code to more than one priority
position (0–7). These bits can be changed dynamically. The definition of SYSB0P is
shown as follows:
000–001 Reserved
010 eSDHC asserts its request in the SYSB0 position.
011–111 Reserved
3–11, 16–27 SYSB1P–SYSB7P Same as SYSB0P, but for SYSB1P–SYSB7P.
12–15, 28–31 — Write ignored, read = 0