Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-14 Freescale Semiconductor
Table 8-10 defines the bit fields of SIPNR_L.
8.5.4 System Internal Interrupt Group A Priority Register (SIPRR_A)
SIPRR_A, shown in Figure 8-6, defines the priority between TSEC1 transmit request (TSEC1 Tx), TSEC1
receive request (TSEC1 Rx), TSEC1 transmit/receive error (TSEC1 Err), and internal interrupt signals.
For more information, see Section 8.6.3, “Internal Interrupts Group Relative Priority.”
14 GTM1_2
15–16 —
17 MSIR2
18 MSIR3
19 —
20 GTM1_3
21 —
22 MSIR4
23 MSIR5
24 MSIR6
25 MSIR7
26 GTM1_1
27–29 —
30 DMAC Err
31 —
Table 8-10. SIPNR_L Field Descriptions
Bits Name Description
0–31 INTn Each implemented bit (listed in Table 8 -9) corresponds to an internal interrupt source. When an interrupt is
received, the interrupt controller sets the corresponding SIPNR bit. When a pending interrupt is handled, the user
clears the SIPNR bit by clearing the corresponding event register bit.
SIPNR bits are read only. Writing to this register has no effect.
Note that the SIPNR bit positions are not changed according to their relative priority.
For unimplemented bits, writes are ignored, read = 0.
Offset 0x10 Access: Read/write
0 2 3 5 6 8 9 1112 1516 1819 2122 2425 2728 31
R
SYSA0P SYSA1P SYSA2P SYSA3P — SYSA4P SYSA5P SYSA6P SYSA7P —
W
Reset00000101001100001001011101110000
Figure 8-6. System Internal Interrupt Group A Priority Register (SIPRR_A)
Table 8-9. SIPNR_L/SIFCR_L/SIMSR_L Bit Assignments (continued)
Bits Field