Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 8-13
Table 8-8 defines the bit fields of SIPNR_H.
SIPNR_L is shown in Figure 8-5.
Table 8-9 lists implemented SIPNR_L fields. Note that these field assignments are also valid for SIFCR_L
and SIMSR_L.
30 I2C2
31 SPI
Table 8-8. SIPNR_H Field Descriptions
Bits Name Description
0–31 INTn Each implemented bit (listed in Table 8 -7) corresponds to an internal interrupt source. When an interrupt is
received, the interrupt controller sets the corresponding SIPNR bit. When a pending interrupt is handled, the
user clears the SIPNR bit by clearing the corresponding event register bit.
SIPNR bits are read only. Writing to this register has no effect.
Note that the SIPNR bit positions are not changed according to their relative priority.
For unimplemented bits, writes are ignored, read = 0.
Offset 0x0C Access: Read only
0 31
R INTn (Implemented bits are listed in Tabl e 8- 9.)
W
Reset All zeros
Figure 8-5. System Internal Interrupt Pending Register (SIPNR_L)
Table 8-9. SIPNR_L/SIFCR_L/SIMSR_L Bit Assignments
Bits Field
0 RTC SEC
1PIT
2—
3MSIR0
4RTC ALR
5—
6 SBA
7—
8GTM1_4
9—
10 GPIO
11 —
12 DDR
13 LBC
Table 8-7. SIPNR_H/SIFCR_H/SIMSR_H Bit Assignments (continued)
Bits Field