Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-12 Freescale Semiconductor
8.5.3 System Internal Interrupt Pending Registers (SIPNR_H and
SIPNR_L)
Each bit in SIPNR_H and SIPNR_L, shown in Figure 8-4 and Figure 8-5, is assigned an internal interrupt
source (implemented bits are listed in Table 8-7). When an interrupt request is received, the interrupt
controller sets the corresponding SIPNR bit. When a pending interrupt is handled, the user clears the
SIPNR bit by clearing the corresponding event register bit.
Note that SIPNR bit positions are not changed according to relative priority.
Table 8-7 lists implemented SIPNR_H fields. Note that these field descriptions are also valid for SIFCR_H
and SIMSR_H.
Offset 0x08 Access: Read only
0 31
R INTn (Implemented bits are listed in Tabl e 8- 7.)
W
Reset All zeros
Figure 8-4. System Internal Interrupt Pending Register (SIPNR_H)
Table 8-7. SIPNR_H/SIFCR_H/SIMSR_H Bit Assignments
Bits Field
0 TSEC1 Tx
1 TSEC1 Rx
2 TSEC1 Err
3 TSEC2 Tx
4 TSEC2 Rx
5 TSEC2 Err
6 USB DR
7–9 —
10 eSDHC
11–15 —
16 PCI Express CNT
17 —
18 DMAC
19 MSIR1
20–23 —
24 UART1
25 UART2
26 —
27 eTSEC1 1588
28 eTSEC2 1588
29 I2C1