Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-10 Freescale Semiconductor
Table 8-6 shows the definition of IVEC.
6–24 — Write ignored, read = 0
25–31 IVEC Regular interrupt vector. Specifies a 7-bit unique number of the IPIC’s highest priority regular interrupt source,
pending to the core. Note that the when a regular interrupt request occurs, SIVCR can be read. If there are
multiple regular interrupt sources, SIVCR latches the highest priority regular interrupt. Note that the IVEC field
correctly reflects all interrupt vectors (see
Ta ble 8 -6 for details).
The value of SIVCR cannot change while it is being read.
Table 8-6. IVEC/CVEC/MVEC Field Definition
Interrupt ID Number Interrupt Meaning Interrupt Vector
0 Error (no interrupt) 0b000_0000
1 PCI Express CNT 0b000_0001
2 Reserved 0b000_0010
3 DMAC 0b000_0011
4 MSIR1 0b0000_0100
5–8 Reserved 0b000_0101–0b000_1000
9 UART1 0b000_1001
10 UART2 0b000_1010
11 Reserved 0b000_1011
12
eTSEC1 1588 0b000_1100
13
eTSEC2 1588 0b000_1101
14
I2C1 0b000_1110
15 I2C2 0b000_1111
16 SPI 0b001_0000
17 IRQ1 0b001_0001
18 IRQ2 0b001_0010
19 IRQ3 0b001_0011
20–31 Reserved 0b001_0100–0b001_1111
32 TSEC1 Tx 0b010_0000
33 TSEC1 Rx 0b010_0001
34 TSEC1 Err 0b010_0010
35
TSEC2 Tx 0b010_0011
36
TSEC2 Rx 0b010_0100
37
TSEC2 Err 0b010_0101
38
USB DR 0b010_0110
39–41 Reserved 0b010_0111–0b010_1001
Table 8-5. SIVCR Field Descriptions (continued)
Bits Name Description