Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
xxviii Freescale Semiconductor
Figures
Figure
Number Title
Page
Number
13-59 Split Transaction State Machine for Isochronous ..............................................................13-111
13-60 Endpoint Queue Head Organization ................................................................................. 13-124
13-61 Endpoint Queue Head Layout........................................................................................... 13-125
13-62 Endpoint Transfer Descriptor (dTD)................................................................................. 13-127
13-63 USB 2.0 Device States...................................................................................................... 13-131
13-64 Endpoint Queue Head Diagram ........................................................................................ 13-143
13-65 Software Link Pointers...................................................................................................... 13-145
13-66 ULPI Timing ..................................................................................................................... 13-156
13-67 Sending of RX CMD......................................................................................................... 13-157
13-68 ULPI Data Transmit (NOPID).......................................................................................... 13-157
13-69 ULPI Data Transmit (PID)................................................................................................ 13-158
13-70 ULPI Data Receive ........................................................................................................... 13-158
13-71 ULPI Register Write.......................................................................................................... 13-159
13-72 ULPI Register Read .......................................................................................................... 13-159
14-1 PCI Express Controller Block Diagram................................................................................ 14-2
14-2 PCI Express PCI Express-Compatible Configuration Header Common Registers ............ 14-14
14-3 PCI Express Vendor ID Register......................................................................................... 14-15
14-4 PCI Express Device ID Register......................................................................................... 14-15
14-5 PCI Express Command Register......................................................................................... 14-16
14-6 PCI Express Status Register................................................................................................ 14-17
14-7 PCI Express Revision ID Register...................................................................................... 14-18
14-8 PCI Express Class Code Register ....................................................................................... 14-18
14-9 PCI Express Bus Cache Line Size Register........................................................................ 14-19
14-10 PCI Express Latency Timer Register.................................................................................. 14-19
14-11 PCI Express Header Type Register..................................................................................... 14-20
14-12 PCI Express PCI Express-Compatible Configuration Header—Type 0............................. 14-21
14-13 32-Bit Base Address Registers (BAR0/BAR1) .................................................................. 14-22
14-14 64-Bit Low Memory Base Address Register (BAR2) ........................................................ 14-23
14-15 64-Bit High Memory Base Address Registers 3 and 5 (BAR3/BAR5).............................. 14-23
14-16 PCI Express Subsystem Vendor ID Register ...................................................................... 14-24
14-17 PCI Express Subsystem ID Register................................................................................... 14-24
14-18 PCI Express Capabilities Pointer Register.......................................................................... 14-25
14-19 PCI Express Interrupt Line Register ................................................................................... 14-25
14-20 PCI Express Minimum Grant Register (MAX_GNT) ........................................................ 14-26
14-21 PCI Express Maximum Latency Register (MAX_LAT)..................................................... 14-26
14-22 PCI Express PCI Express-Compatible Configuration Header—Type 1............................. 14-27
14-23 PCI Express Primary Bus Number Register ....................................................................... 14-27
14-24 PCI Express Secondary Bus Number Register ................................................................... 14-28
14-25 PCI Express Subordinate Bus Number Register................................................................. 14-28
14-26 PCI Express I/O Base Register ........................................................................................... 14-29
14-27 PCI Express I/O Limit Register .......................................................................................... 14-29