Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 8-9
8.5.2 System Global Interrupt Vector Register (SIVCR)
SIVCR, shown in Figure 8-3, contains a 7-bit code (Table 8-5) representing the regular unmasked interrupt
source (INT) of the highest priority level.
NOTE
Note that in core disabled mode the user should use SIVCR only in order to
read an updated interrupt vector (SCVCR and SMVCR should not be used).
Table 8-5 defines the bit fields of SIVCR.
16–21 — Write ignored, read = 0
22–23 HPIT HPI priority position IPIC output interrupt type. Defines which type of IPIC output interrupt signal (int
, cint, or
smi
) asserts its request to the core in the HPI priority position. These bits cannot be changed dynamically. (If
software really wants to change it, it has to make sure the corresponding interrupt source is masked or it won’t
happen during the change).
The definition of HPIT is as follows:
00 int
request is asserted to the core for HPI.
01 smi
request is asserted to the core for HPI.
10 cint request is asserted to the core for HPI.
11 Reserved.
24–31 — Write ignored, read = 0
Offset 0x04 Access: Read only
056 24 25 31
R IVECx
—
IVEC
W
Reset All zeros
Figure 8-3. System Global Interrupt Vector Register (SIVCR)
Table 8-5. SIVCR Field Descriptions
Bits Name Description
0–5 IVECx Backward (MPC8260) compatible regular interrupt vector. Specifies a 6-bit unique number of the IPIC’s highest
priority regular interrupt source, pending to the core. When a regular interrupt request occurs, SIVCR can be
read. If there are multiple regular interrupt sources, SIVCR latches the highest priority regular interrupt. Note
that IVECx field correctly reflects only the first 64 interrupt vectors (See Tabl e 8- 6 for details).
The value of SIVEC cannot change while it is being read.
Table 8-4. SICFR Field Descriptions (continued)
Bits Name Description