Information
Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 8-7
0x010 System internal interrupt group A priority register (SIPRR_A) R/W 0x0530_9770 8.5.4/8-14
0x014 System internal interrupt group B priority register (SIPRR_B) R/W 0x0530_9770 8.5.5/8-15
0x018 System internal interrupt group C priority register (SIPRR_C) R/W 0x0530_9770 8.5.6/8-16
0x01C System internal interrupt group D priority register (SIPRR_D) R/W 0x0530_9770 8.5.7/8-16
0x020 System internal interrupt mask register (SIMSR_H) R/W 0x0000_0000 8.5.8/8-17
0x024 System internal interrupt mask register (SIMSR_L) R/W 0x0000_0000 8.5.8/8-17
0x028 System internal interrupt control register (SICNR) R/W 0x0000_0000 8.5.9/8-18
0x02C System external interrupt pending register (SEPNR) R/W Special 8.5.10/8-20
0x030 System mixed interrupt group A priority register (SMPRR_A) R/W 0x0530_9770 8.5.11/8-21
0x034 System mixed interrupt group B priority register (SMPRR_B) R/W 0x0530_9770 8.5.12/8-22
0x038 System external interrupt mask register (SEMSR) R/W 0x0000_0000 8.5.13/8-22
0x03C System external interrupt control register (SECNR) R/W 0x0000_0000 8.5.14/8-23
0x040 System error status register (SERSR) R/W 0x0000_0000 8.5.15/8-25
0x044 System error mask register (SERMR) R/W see section 8.5.16/8-25
0x048 System error control register (SERCR) R/W 0x0000_0000 8.5.17/8-26
0x04C System external interrupt polarity control register (SEPCR) R/W 0x0000_0000 8.5.18/8-26
0x04F Reserved — — —
0x050 System internal interrupt force register (SIFCR_H) R/W 0x0000_0000 8.5.19/8-27
0x054 System internal interrupt force register (SIFCR_L) R/W 0x0000_0000 8.5.19/8-27
0x058 System external interrupt force register (SEFCR) R/W 0x0000_0000 8.5.20/8-29
0x05C System error force register (SERFR) R/W 0x0000_0000 8.5.21/8-29
0x060 System critical interrupt vector register (SCVCR) R 0x0000_0000 8.5.22/8-30
0x064 System management interrupt vector register (SMVCR) R 0x0000_0000 8.5.23/8-30
0x068–0x0BF Reserved — — —
Table 8-3. IPIC Register Address Map (continued)
Offset Register Access Reset Value
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