Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-6 Freescale Semiconductor
8.5 Memory Map/Register Definition
The IPIC programmable register map occupies 256 bytes of memory-mapped space. Reading undefined
portions of the memory map returns all zeros; writing has no effect.
All IPIC registers are 32 bits wide and they are located on 32-bit address boundaries. Software can perform
byte, half-word, or word accesses to any IPIC registers. All addresses used in this chapter are offsets from
the IPIC base, as defined in Chapter 3, “Memory Map.”
Table 8-3 shows the memory map of the IPIC unit.
MCP_OUT OD Non-maskable Interrupt (machine check) request out. Active-low, open drain. When the IPIC is programmed
in core disable mode, this output reflects the mcp
interrupts generated by on-chip sources. See Section 8.3,
“Modes of Operation.”
State
Meaning
Asserted—At least one machine check interrupt is currently being signaled to the external
system.
Negated—Indicates no interrupt source currently routed to MCP_OUT
.
Timing Because external interrupts are asynchronous with respect to the system clock, both
assertion and negation of MCP_OUT occurs asynchronously with respect to the interrupt
source. All timing given here is approximate.
Assertion—Internal interrupt source: 2 system bus clock cycles after interrupt occurs. External
interrupt source: 4 cycles after interrupt occurs.
Negation—Follows interrupt source negation with the following delay:
Internal interrupt: 2 system bus clock cycles. External interrupt: 4 cycles.
Table 8-3. IPIC Register Address Map
Offset Register Access Reset Value
Section/
Page
Integrated Programmable Interrupt Controller—Block Base Address 0x0_0700
0x000 System global interrupt configuration register (SICFR) R/W 0x0000_0000 8.5.1/8-8
0x004 System regular interrupt vector register (SIVCR) R 0x0000_0000 8.5.2/8-9
0x008 System internal interrupt pending register (SIPNR_H) R 0x0000_0000 8.5.3/8-12
0x00C System internal interrupt pending register (SIPNR_L) R 0x0000_0000 8.5.3/8-12
Table 8-2. IPIC External Signals—Detailed Signal Descriptions (continued)
Signal I/O Description
INTA OD Interrupt request out. Active-low, open drain. When the IPIC is programmed in core disable mode, this output
reflects the raw interrupts generated by on-chip sources. See Section 8.3, “Modes of Operation” for details.
State
Meaning
Asserted—At least one interrupt is currently being signalled to the external system.
Negated—Indicates no interrupt sources currently routed to INTA
.
Timing Because external interrupts are asynchronous with respect to the external clock, both assertion
and negation of INTA
occur asynchronously with respect to the interrupt source. All timing
given here is approximate.
Assertion—Intrernal interrupt source: 3 system bus clock cycles after the interrupt occurs.
External interrupt source: 4 cycles after the interrupt occurs.
Negation—Follows interrupt source negation with the following delay:
Internal interrupt: 3 system bus clock cycles. External interrupt: 4 cycles.